Back to Microchip Technology

Microchip Technology SMC 2000 Smart Memory Controllers

Microchip Technology SMC 2000 Smart Memory Controllers are Compute Express Link (CXL) Type-3 memory controllers designed to meet the growing memory bandwidth and capacity demands of data center workloads. The SMC 2000 components support the CXL 1.1 and CXL 2.0 specifications utilizing CXL.mem sub-protocol for low-latency memory expansion and the CXL.io sub-protocol for management. The low-latency SMC 2000 16×32G and SMC 2000 8×32G memory controllers are designed to CXL 1.1 and CXL 2.0 specifications, comply with DDR4 and DDR5 JEDEC standards, and support PCIe® 5.0 specification speeds. The SMC 2000 16×32G offers 16 lanes operating at 32 GT/s with two channels of DDR4-3200 or DDR5-4800, resulting in a significant reduction in the required number of host CPUs or SoC pins per memory channel. Applications include AI, ML, High-Performance Computing (HPC), and other applications that require an increased number of memory channels to deliver more memory bandwidth and capacity.

Features

  • High-performance, low-latency DRAM bandwidth and capacity expansion
  • High-reliability CXL with robust error containment, end-to-end data integrity protection and ECC protection on internal and external memories
  • Industry-leading security with Root of Trust (RoT), secure boot, secure firmware updates, secure debug, firmware encryption, and attestation features
  • CXL
    • CXL 1.1- and CXL 2.0-capable Type-3 memory controller
    • Options
      • Up to 1x16 32Gbps CXL (PM8702 SMC 2000 16x32G)
      • Up to 1x8 32Gbps CXL (PM8701 SMC 2000 8x32G)
    • Common clock (with/without SSC) and separate clock (SRIS/SRNS)
    • CXL interleaving support of 1/2/4/8-way with granularity from 256B to 16KB
    • L0 (normal) and L1 low-power control state
    • SLD support with up to 16 logical devices
    • Device-level reset pin (RSTB) and CXL port-level reset (PERST)
    • Up to 512B maximum payload size (MPS)
  • DDR
    • 2x DDR controllers with DDR4 and DDR5 support
    • 2x 40-bit DDR5 interface or 1x 72-bit DDR4 interface per DDR controller
    • Up to 4H 3DS stack per DDR controller
    • Up to 4x logical ranks per DDR controller
    • Support for 4x or 8x DRAM devices
  • Reliability, availability, and serviceability (RAS)
    • End-to-end data path integrity with overlapping parity/ECC
    • Industry-leading ECC support for DDR
    • Chip kill support
    • Programmable patrol scrub
    • DRAM memory initialization at boot
    • Transparency mode/ECS
    • Refresh Management (RFM) for row hammer mitigation
    • Post package repair (sPPR and hPPR)
    • Programmable memory BIST
    • Thermal performance throttling
  • Diagnostics
    • CXL and DDR performance monitors, error counters, error injection, and trace
    • LTSSM log and triggers
    • Ordered set analyzer
    • Firmware logs, crash dump, and event records
  • Security
    • Secure boot, firmware update, and debug
    • Device personalization/certificates
    • Attestation
    • Key management
    • Firmware encryption
  • Peripheral support for SPI, I3C/I2C, GPIO, UART, and JTAG/EJTAG
  • Package options
    • 19mm2 package for SMC 2000 8x32G
    • 25mm2 package for SMC 2000 16x32G

Applications

  • Artificial Intelligence (AI)
  • High bandwidth memory in data center servers/storage products
  • Machine Learning (ML)
  • Off-the-shelf CXL DRAM-based EDSSF drives

Block Diagram

Block Diagram - Microchip Technology SMC 2000 Smart Memory Controllers
Published: 2022-08-08 | Updated: 2022-09-29